Design of electronic circuits and chips, for example, an integrated circuit (IC) involves a variety of steps. FIG. 1 illustrates a typical design flow 100 of an integrated circuit device from conception through the generation of a fabrication-ready design layout. Generally, design flow 100 begins at 102 with defining the design specifications or requirements, such as required functionality and timing. The requirements of the design are implemented, for example, as a net-list or electronic circuit description, at 104. The implementation can be performed by, for example, schematic capture (drawing the design with a computer aided design tool) or utilizing a high level description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL), Verilog® and the like. At 106, the implemented design is simulated to verify design accuracy. Design implementation and simulation are iterative processes. For example, errors found by simulation are corrected by design implementation and re-simulated.
Once the design is verified for accuracy with simulation, a design layout of the design is created, at 108. The design layout describes the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication. The design layout is associated with overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances, and the silicon area that is used to realize a certain function. The detailed design layout requires design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
The design layout is checked against a set of design rules in a design rule check (DRC), step 110. The created design layout is intended to conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart various layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule can be, for example, a minimum spacing amount between geometries and is typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries can be specified for different sizes of geometries. DRC is a time-consuming iterative process that conventionally often requires manual manipulation and interaction by the designer. The designer performs design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC clean (violation free) design. Among the design rules that exist are design rules for metal enclosures for vias. For example, some such design rules are asymmetric metal enclosure rules, which require more metal enclosure at the metal path end, while allowing less metal enclosure at the metal path side.
Circuit extraction is performed after the design layout is completed and error free, at 112. The extracted circuit identifies individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present between the layers. A layout versus schematic (LVS) check is performed, at 114, where the extracted net-list is compared to the design implementation created at 104. LVS ensures that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, or the like are corrected in the design layout before proceeding to post-layout simulation, at 116. The post-layout simulation is performed using the extracted net-list which provides a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that can occur due to signal delay mismatches. Once post-layout simulation is complete and all errors found by DRC are corrected, the design is ready for fabrication and is sent to a fabrication facility.
As electronic circuit densities increase and technology advances, for example, in deep-sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and the manufacturability and reliability of the circuit. Deep-sub-micron designs typically have stringent design rules that are often not recognized by EDA tools, for example, automated place and route tools. Therefore, when creating a design layout in step 108, for example, many design rule violations can be created that must be corrected.
One area where design rules have become particularly important is in the area of metal layers and vias. A via is used to connect, for example, two design geometries, one on each of two consecutive conductive layers (e.g., a metal line on each of two consecutive metal layers) of an electronic circuit. For example, it can be important to ensure that each connection area between two conductive layers has at least a certain number of vias and/or has vias placed appropriately to reduce the risk of via failure due to vacancy concentration of isolated vias.